The present invention relates generally to memory systems such as a flash memory array system. More particularly, the present invention relates to an improved negative regulator circuit for a negative charge pump circuit, wherein a voltage divider circuit uses MOS capacitors, and a bias circuit which supplies a bias voltage used in association with the MOS capacitors insuring they operate at voltages which will maintain a minimum target capacitance. The regulated negative voltage may be applied to a wordline, for example, for erase mode operations of memory cells.
Flash and other types of electronic memory devices are constructed of thousands or millions of memory cells, adapted to individually store and provide access to data. A typical memory cell stores a single binary piece of information referred to as a bit, which has one of two possible states. The cells are commonly organized into multiple cell units such as bytes which comprise eight cells, and words which may include sixteen or more such cells, usually configured in multiples of eight. Storage of data in such memory device architectures is performed by writing to a particular set of memory cells, sometimes referred to as programming the cells. Retrieval of data from the cells is accomplished in a read operation. In addition to programming and read operations, groups of cells in a memory device may be erased, wherein each cell in the group is programmed to a known state.
The individual cells are organized into individually addressable units or groups such as bytes or words, which are accessed for read or program operations through address decoding circuitry, whereby such operations may be performed on the cells within a specific byte or word. The individual memory cells are typically comprised of a semiconductor structure adapted for storing a bit of data. For instance, many conventional memory cells include a metal oxide semiconductor (MOS) device, such as a transistor in which a binary piece of information may be retained. The memory device includes appropriate decoding and group selection circuitry to address such bytes or words, as well as circuitry to provide voltages to the cells being operated on in order to achieve the desired operation.
The erase, program, and read operations are commonly performed by application of appropriate voltages to certain terminals of the cell MOS device. In an erase or program operation the voltages are applied so as to cause a charge to be stored in the memory cell. In a read operation, appropriate voltages are applied so as to cause a current to flow in the cell, wherein the amount of such current is indicative of the value of the data stored in the cell. The memory device includes appropriate circuitry to sense the resulting cell current in order to determine the data stored therein, which is then provided to data bus terminals of the device for access to other devices in a system in which the memory device is employed.
Flash memory is a type of electronic memory media which can be rewritten and hold its content without power. Flash memory devices generally have life spans from 100 K to 1 MEG write cycles. Unlike dynamic random access memory (DRAM) and static random access memory (SRAM) memory chips, in which a single byte can be erased, flash memory is typically erased and written in fixed multi-bit blocks or sectors. Conventional flash memories are constructed in a cell structure wherein a single bit of information is stored in each flash memory cell. In such single bit memory architectures, each cell typically includes a MOS transistor structure having a source, a drain, and a channel in a substrate or P-well, as well as a stacked gate structure overlying the channel. The stacked gate may further include a thin gate dielectric layer (sometimes referred to as a tunnel oxide) formed on the surface of the P-well. The stacked gate also includes a polysilicon floating gate overlying the tunnel oxide and an interpoly dielectric layer overlying the floating gate. The interpoly dielectric layer is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer. Lastly, a polysilicon control gate overlies the interpoly dielectric layer.
FIG. 1 illustrates a typical NOR configuration 100, wherein the control gate 110 is connected to a word line (e.g., WL0 thru WL3) associated with a row of such cells 120 to form sectors of such cells. In addition, the drain regions 130 of the cells are connected together by a conductive bit line (e.g., BL0 thru BL3). The channel of the cell conducts current between the source 140 and the drain 130 in accordance with an electric field developed in the channel by the stacked gate structure. In the NOR configuration, each drain terminal 130 of the transistors 120 within a single column is connected to the same bit line. In addition, each flash cell 120 associated with a given bit line has its stacked gate terminal 110 coupled to a different word line (e.g., WL1 thru WL4), while all the flash cells in the array have their source terminals 140 coupled to a common source terminal (CS). In operation, individual flash cells 120 are addressed via the respective bit line and word line using peripheral decoder and control circuitry for programming (writing), reading or erasing functions.
Such a single bit stacked gate flash memory cell is programmed, for example, by applying a relatively high voltage to the control gate and connecting the source to ground and the drain to a predetermined potential above the source. A resulting high electric field across the tunnel oxide leads to a phenomena called xe2x80x9cFowler-Nordheimxe2x80x9d tunneling. During this process, electrons in the core cell channel region tunnel through the gate oxide into the floating gate and become trapped in the floating gate since the floating gate is surrounded by the interpoly dielectric and the tunnel oxide. As a result of the trapped electrons, the threshold voltage of the cell increases. This change in the threshold voltage (and thereby the channel conductance) of the cell created by the trapped electrons is what causes the cell to be programmed.
In order to erase a typical single bit stacked gate flash memory cell, a relatively high voltage is applied to the source, and the control gate is held at a negative potential, while the drain is allowed to float. Under these conditions, a strong electric field is developed across the tunnel oxide between the floating gate and the source. The electrons that are trapped in the floating gate flow toward and cluster at the portion of the floating gate overlying the source region and are extracted from the floating gate and into the source region by way of Fowler-Nordheim tunneling through the tunnel oxide. As the electrons are removed from the floating gate, the cell is erased.
For a read operation, a certain voltage bias is applied across the drain to source of the cell transistor. The drain of the cell is the bit line, which may be connected to the drains of other cells in a byte or word group. The voltage at the drain in conventional stacked gate memory cells is typically provided at between 0.5 and 1.0 volts in a read operation. A voltage is then applied to the gate (e.g., the word line) of the memory cell transistor in order to cause a current to flow from the drain to source. The read operation gate voltage is typically applied at a level between a programmed threshold voltage (VT) and an unprogrammed threshold voltage. The resulting current is measured, by which a determination is made as to the data value stored in the cell.
More recently, dual bit flash memory cells have been introduced, which allow the storage of two bits of information in a single memory cell. The bitline (drain), and wordline (gate) voltages required for dual bit memory cells is typically higher than that of single bit, stacked gate architecture memory cells, due to the physical construction of the dual bit cell.
In these semiconductor applications, a charge pump sometimes is used to increase a small input, or supply voltage (for example, VCC) to a larger voltage that is passed to the word lines or bit lines of the semiconductor memory devices. For example, some dual bit memory cell architectures require about 9.5 volts to properly bias the word lines, about 6 volts for the bitline or drain of such cells, and between xe2x88x926 to xe2x88x928 volts for negative erase voltages, for the various memory operations discussed. These voltages which are all higher than the applied supply voltage, are all created and fed by charge pumps to increase the supply voltage to the output voltage desired. These voltages affect the reading, writing, and erasing of data from/to the memory device, and as such, often need the addition of a regulation circuit to maintain the accuracy of the charge pump output voltage for the various memory operations.
Because these charge pump voltages applied to the memory cell are derived from the memory device supply voltage (VCC), the ability to provide the higher voltage required for the newer dual bit memory cells may be impaired when the supply voltage is at or near lower rated levels. In addition, low power applications for memory devices, such as cellular telephones, laptop computers, and the like, may further reduce the supply voltage available. To overcome the extremes of input VCC voltages applied to a charge pump and the variations which would otherwise be reflected in the output, a charge pump regulation circuit will also be employed.
Currently, conventional regulation circuits for charge pumps are constructed using several types of voltage dividers. As the required voltages for applications increases, the number of stages necessary to generate the higher output voltages also increases.
FIG. 2 provides an illustration of a conventional negative regulation circuit for a charge pump. The conventional negative charge pump regulator 200 regulates the output NEGP 240 of the negative charge pump 235. The output of the charge pump is divided down across a conventional metal-oxide-metal capacitor voltage divider C1 (250) and C2 (255) to produce a voltage divider voltage VDIV. VDIV 265 is compared to ground 270 in the differential amplifier comparator 260 to yield a comparison result VCOMP 275, which is applied as feedback to the gate of an output transistor 278. When the charge pump output tries to go lower than some target regulation voltage, the regulator output transistor 278 turns-on to pull the negative charge pump 235 output NEGP 240 up. When the charge pump output goes higher than the target regulation voltage, the output transistor 278 will turn-off to allow the negative charge pump output to continue down to a lower voltage.
The conventional negative charge pump regulator 200 also has a VREF input 225 and a PRECHARGE transistor input 220, provided for initializing the capacitors in the voltage divider to a predetermined value VREF 225. Unlike a resistor voltage divider which has a continuous DC self biasing, a capacitor divider must be preset or precharged to a predetermined initial voltage so the voltage divider can function properly. In the conventional negative charge pump regulator 200, VREF 225 is coupled to C1 (250) and C2 (255) to initially apply VREF across each of the capacitors, when NEGP is initially at ground.
In operation, the negative pump regulator 200, will initialize the capacitive divider by precharging C1 (250) and C2 (255) thru transistor 245 to the voltage at VREF 225.
Initially, the NEGP output 240 of the charge pump 235 is at ground potential. After the precharge interval, the charge pump is enabled and will begin to charge. The negative regulator 200, will begin to regulate the output voltage at NEGP 240 when the voltage at the VDIV 265 non-inverting terminal has been pulled down to about zero volts (roughly equaling the same voltage which is on the inverting terminal 270 of the comparator). Note that at this point of regulation, that the voltage across C1 is zero volts, while the voltage across C2 is the negative pump output voltage NEGPxe2x88x92VDIV=NEGPxe2x88x920=NEGP.
FIG. 3 is an illustration of the conventional metal-oxide-metal capacitors which are used in the capacitor voltage divider of the conventional negative regulator circuit of FIG. 2. The conventional metal capacitor 280, is basically two metal plates M1 (294) and M2 (290) separated by an oxide insulation layer 292. The conventional metal capacitor 280 is isolated by another oxide insulation layer 296 from the base substrate material 285. The oxide layer 292 acts as the dielectric material for the capacitor, and must be made relatively thick in the metal-oxide-metal capacitor manufacturing. Because of the thickness of this dielectric, the conventional metal capacitors must be large, and therefore require a large area of the semiconductor for the conventional negative regulator using these metal capacitors.
As most device applications seek to consume a minimum of semiconductor die area to keep the size of a device down, size becomes particularly important in portable device applications. Accordingly, there is a need for reducing the area required for a negative regulator used in conjunction with a negative charge pump circuit, while maintaining a low power, simple regulator design.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended neither to identify key or critical elements of the invention nor to delineate the scope of the invention. Its primary purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The invention is directed to an improved, reduced area negative regulator circuit for a negative charge pump where one or more capacitors of the negative regulator voltage divider is characterized by having a MOS capacitor, and a bias circuit which supplies a bias voltage used in association with the MOS capacitors insuring they operate above a minimum voltage which will maintain a minimum target capacitance.
In the present invention of flash memory array systems and methods for producing a negative charge pump regulator circuit with reduced area, the use of MOS capacitors is employed in the voltage divider of a negative regulator circuit applied to a negative charge pump circuit which may be used to generate a negative voltage for various operations of memory cells.
MOS capacitors are preferred over metal-oxide-metal (MOM) capacitors, as MOS capacitors only require about {fraction (1/10)}th the area of the same value MOM capacitor. This dramatic increase in capacitance per unit area is possible with the MOS capacitor, because MOS capacitors are able to be manufactured with a much thinner SiO2 (Silicon Dioxide) dielectric insulating layer. MOS capacitors however, unlike MOM capacitors, are still semiconductors requiring a bias voltage across their plates to prevent their capacitance value from dropping too low. The present invention overcomes this limitation with a bias circuit which generates this bias voltage on the MOS capacitors to maintain a minimum target capacitance, while taking advantage of the area savings of MOS capacitors.
Simply, the bias circuit generates a bias voltage to a differential amplifier in the regulator for comparison to a voltage produced by the voltage divider circuit. As circuit feedback to the differential amplifier seeks to zero the difference across its inputs, the bias voltage insures that the voltage generated at the voltage divider circuit will also oscillate about the bias voltage value during regulation. In this way, the bias voltage insures that at a minimum, an equivalent voltage is also applied to the capacitors in the voltage divider, and a minimum target capacitance is maintained.
The negative regulator also contains an initialization circuit which precharges the voltage divider capacitors to a reference voltage. An output circuit is also provided to shunt the output of the charge pump to the supply voltage (e.g., VCC) when the output attempts to go lower than a predetermined regulation voltage.
Thus, a feature of the negative regulator of the present invention is that it requires less area than conventional negative charge pump regulators, as the MOS capacitors which are used in the voltage divider can be made much smaller in area than comparable MOM capacitors, thereby substantially reducing the area required for the negative regulator.
An advantage of the present invention is the ability of the negative regulator system to produce a more accurate voltage divider output, as compared to a conventional MOS capacitor voltage divider systems without the bias voltage. Without this bias circuit voltage, a conventional system based on the MOS capacitor, would experience widely varying voltage divider ratios over the range of regulation voltages it encountered, resulting in a widely varying output regulation voltage.
According to one aspect of the present invention, a sense and control circuit is included to provide capacitance selection to a capacitor of the capacitive voltage divider, to permit adjustment of the voltage divider ratio, and the resultant negative output voltage value. For example, where manufacturing tolerances of the capacitor values may vary over a wide range, the selection of a combination of trimming capacitors may provide better accuracy in the divider. Consequently, the present invention provides a negative regulator with a reduced area for regulating a charge pump output voltage, for example, a wordline voltage, which facilitates accurate operation of flash memory cells despite fluctuations in the load, supply voltage, or the charge pump.
The aspects of the invention find application in devices which include dual bit memory cells requiring higher bitline and wordline voltages than single bit cells, and in association with portable memory devices employed in varying supply voltage and low power applications.
To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.